The present invention generally relates to write circuits, and more particularly to a write circuit for a non-volatile memory device which writes information by causing an avalanche breakdown of a cell transistor.
In a non-volatile memory device such as an erasable programmable read only memory (EPROM), data is written by applying a high voltage to the control gate and the drain of a transistor which forms a memory cell. The write efficiency of such a write operation is dependent on the drain voltage, and it is necessary to maintain the drain voltage at an appropriate value.
FIG. 1 shows an example of a conventional write circuit together with related parts of the EPROM. In FIG. 1 and figures which follow, a depletion type MOS transistor is indicated with a dot beside its drain.
In FIG. 1, depletion type MOS transistors Q1 and Q2 are used for supplying a power source voltage to a column decoder, transistors Q3 and Q4 form an inverter within the column decoder, a transistor Q5 is used for supplying a power source voltage for programming (writing), a transistor Q6 is used for bit line selection, and a transistor Q7 forms a EPROM cell.
When programming the EPROM, an output signal of a NAND circuit 10 has a low level in response to a column address, and a high voltage Vpp of 12.5 V is applied to the gate of the cell transistor Q7, that is, through a word line WL. In addition, a program signal PGM has a high level and an inverted program signal PGM has a low level, and the voltage Vpp is supplied to the column decoder as the power source voltage. Accordingly, the voltage Vpp is supplied to both the gate and the drain of the cell transistor Q7, and a write operation is carried out.
A characteristic I indicated by a solid line I in FIG. 2 shows a breakdown characteristic of the cell transistor Q7 described by a drain current I.sub.D and a drain voltage V.sub.D. On the other hand, a characteristic II indicated by a solid line shows a drain current I.sub.D versus drain voltage VD characteristic (that is, a load curve) of the select transistor Q6. The write operation is carried out with respect to the cell transistor Q7 at an intersection point A between the two characteristics I and II.
However, if the gate length of the cell transistor Q7 is shorter than a designed value, due to inconsistencies introduced from inevitable production error, the breakdown characteristic of the cell transistor Q7 changes as indicated by a dotted line III in FIG. 2, and in this case, the write operation with respect to the cell transistor Q7 is carried out at an intersection point B between the characteristics II and III. In this case, the breakdown of the cell transistor Q7 occurs in a tunnel region and not in an avalanche region. Because the electron energy is small in the tunnel region, the electrons do not penetrate the oxide layer barrier thereby to accumulate a charge in the floating gate of the cell transistor Q7, and thus, there is a problem in that the write efficiency becomes poor. In addition, when the drain current I.sub.D becomes large, there is a problem in that the transistors Q6 and Q7 may break down.